Competent Universal Reversible Logic Gate Design for Quantum dot Cellular Automata

Quantum dot cellular Automata (QCA) is leading technology for alternative of CMOS design. Reversible Logic design is found to be Low power design which becomes emerging technology in Low power Nanotechnology era. In this work we devoted to design a Reversible Logic Gate which is a universal gate (known as URLG) and can be design with alternative of co-planer cross over wire. We introduce a passive type 3×3 tile that will also helpful for design the co-planner crossover wire, implements Reversible gate. We analyzed the application of passive type tile with the implementation of proposed URLG. The reversible gate design proposed in this paper which is proved to be universal by means of designing all classical logic gate i.e. AND, OR, NOT, NAND, NOR and XOR. During design of URLG we made attention is to reduce the no.’s of cells as well as to reduce the area which is found to be 0.16μm2 with conventional co-planner crossover wire and 0.19 μm2 area with new proposed passive 3×3 tile and compared to Fredkin gate it achieved 48%(on average) reduction in area (area of Fredkin gate is 0.37 μm2). We also tried made focus on ‘Garbage Minimization’ Problem. Here, we demonstrate that the design all Logic gate generate low garbage output as we make a comparison with NFT gate. We achieve 20% reduction in garbage count. The competent design of working Temperature, Fault Tolerant URLG is useful to implement all combinational Logic circuit as well as sequential circuit. Hence, it shall be innovative, effective with respect to previous report.